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VIS
Description
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank, 4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations provide wide choice for different applications. It is designed with the state-of-the-art technology to meet standard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the performance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
* Single 3.3V ( 0.3V) power supply * High speed clock cycle time : 7.5ns/10ns * Fully synchronous with all signals referenced to a positive clock edge * Programmable CAS Iatency (2,3) * Programmable burst length (1,2,4,8,& Full page) * Programmable wrap sequence (Sequential/Interleave) * Automatic precharge and controlled precharge * Auto refresh and self refresh modes * Quad Internal banks controlled by BA0 & BA1 (Bank select) * Each Bank can be operated simultaneously and independently * I/O level : LVTTL compatible * Random column access in every cycle * x4, x8, x16 organization * Input/Output controlled by DQM ( LDQM, UDQM ) * 4,096 refresh cycles/64ms * Burst termination by burst stop and precharge command * Burst read/single write option
The information shown is subject to change without notice.
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Pin Configuration
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
VG36128401 (X 4) VG36128801 (X 8) VG36128161 (X 16)
VDD NC VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC
NC VDD NC
WE CAS RAS CS
NC VDD NC
WE CAS RAS CS
VDD LDQM
WE CAS RAS CS
BA0 BA1 A10 A0 A1 A2 A3 VDD
BA0 BA1 A10 A0 A1 A2 A3 VDD
BA0 BA1 A10 A0 A1 A2 A3 VDD
A11
A9 A8 A7 A6 A5 A4 VSS
A11
A9 A8 A7 A6 A5 A4 VSS
A11
A9 A8 A7 A6 A5 A4 VSS
Pin Description VG36128801/VG36128161 Pin Name A0 - A11 BAO, BA1 DQ0 ~ DQ15 RAS CAS WE VSS VDD
Function
Pin Name DQM, LDQM, UDQM, CLK CKE CS VDDQ VSSQ
Function Upper DQ Mask enable, Lower DQ Mask enable Clock input Clock enable Chip select Supply voltage for DQ Ground for DQ
Address inputs Bank select Data - in/data - out Row address strobe Column address strobe Write enable Ground Power (+ 3.3V)
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Block Diagram
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
CLK CKE
Clock Generator
Address
Mode Register
Row Decoder
Row Address Buffer & Refresh Counter
(Bank D) (Bank C) Bank B
Bank A
Sense Amplifier
Command Decoder
RAS CAS WE
Control Logic
CS
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
DQ
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Absolute Maximum D.C. Ratings Parameter Voltage on any pin relative to Vss
Supply voltage relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Symbol VIN, VOUT VDD, VDDQ IOUT PD T OPT T STG
Value -0.5 to + 4.6 -0.5 to + 4.6 50 1.0 0 to + 70 -55 to + 125
Unit V V mA W J J
Caution:
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Maximum A.C. Operating Requirements for LVTTL Compatible Parameter Symbol Min Input High Voltage VIH 2.0
Input Low Voltage VIL -0.3
Max VDD + 0.3 0.8
Unit V V
Notes 1 2
Note: 1. Overshoot limit: VIH(max)=VDDQ +2.0V with a pulse with
< 3ns 2. Undershoot limit: VIL(min)=VSSQ -2.0V with a pulse with < 3ns
and -1.5v with a pulse < 5ns
Recommended DC Operating Conditions for LVTTL Compatible Parameter Symbol Min Supply Voltage VDD, VDDQ 3.0
Input High Voltage, all inputs Input Low Voltage, all inputs VIH VIL 2.0 -0.3
Typ 3.3
Max 3.6 VDD + 0.3 0.8
Unit V V V
Capacitance (Ta=25C, f = 1MHZ)
Parameter Input capacitance (CLK) Input capacitance (all input pins except data pins.) Data input/output capacitance
Symbol C11 C12 CI/O
Min 2.5 2.5 4.0
Max 4 5 6.5
Unit pF pF pF
Notes 1 1 1
Notes : 1. Capacitance measured with effective capacitance measuring method.
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Parameter Operating current Precharge standby current in Power down mode Precharge standby current in Nonpower down mode ICC2P ICC2PS ICC2N Symbol ICC1
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
-75 Test Conditions Burst length = 1 One bank active tRC tRC(MIN.), Io = 0mA x4 x8 x16 Min Max 120 125 135 2 2 20 Min
-8H Max 100 105 115 2 2 20
Unit mA
Notes 1
VIL(MAX.) tCK = min. CKE VIL(MAX.) tCK =
CKE CKE VIH(MIN.) tCK = min. CS VIH(MIN.) Input signals are changed one time during 2 CLK cycles.
mA
mA
ICC2NS
CKE VIH(MIN.) tCK = CLK VIL(MAX.) Input signals are stable.
7
7
Active standby current ICC3P in Power ICC3PS down mode ICC3N Active standby current in Nonpower down mode
VIL(MAX.) tCK = min. CKE VIL(MAX.) tCK =
CKE CKE VIH(MIN.) tCK = min. CS VIH(MIN.) Input signals are changed one time during 2CLKs CKE VIH(MIN.) tCK = CLK VIL(MAX.) Input signals are stable.
7 5 30
7 5 30
mA
mA
ICC3NS
20
20
Operating current (Burst mode) Refresh current Self refresh Current Input Ieakage current (Inputs) Intput leakage current (I/O pins) Output Low Voltage Output High Voltage
ICC4
tCK tCK(MIN.) Io = 0mA All banks Active tRC = 4 x tRC(MIN) CKE 0.2V VIN 0, VIN VDD(MAX.) Pins not under test = 0V VOUT 0, VOUT IOL = 2mA IOH = -2mA
x4 x8 x16
ICC5 ICC6 lLI lLO VOL VOH
115 130 160 190 1 -1 -1.5 1 1.5 0.4 2.4 2.4 -1 -1.5
105 120 150 190 1 1 1.5 0.4
mA mA mA uA uA V V
2 3
VDD(MAX.)
DQ# in H - Z., Dout Disabled
4 4
Notes : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, I CC1 is measured on condition that addresses are changed only one time during tCK(MIN.). 2. I CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.). 3. I CC5 is measured on condition that addresses are changed only one time during tCK(MIN.). 4. For LVTTL compatible.
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Test Conditions for LVTTL Compatible :
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
AC Characteristics : (Ta = 0 to 70C V DD = 3.3V 0.3V ,VSS = 0V)
AC input Levels (VIH/VIL) Input rise and fall time
2.0/0.8V 1ns
Input timing reference level/ Output timing reference level Output load condition
1.4V 50pF
AC Test Load Circuits (for LVTTL interface) :
VDDQ VOUT
VDDQ
Z = 50
50PF
Device Under Test
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symbol tRC tRCD tRP tRRD tRAS tCK2 tCK3 tCH tCL tAC2 tAC3 tT tCCD tOH tLZ tHZ2 tHZ3 tIS tIH tSRX tPDE tRSC tDPL tDAL2 tDAL3 tBDL tREF Last data in to burst stop Refresh time Data output high impedance Data/Address/Control Input setup time Data/Address/Control Input hold time Minimum CKE "High"for Self-Refresh exit Power Down Exit set-up time Mode Register Set Cycle Data-in to precharge Data-in to ACT (REF) Command Clock cycle time Clock high time Clock low time Access time from CLK (positive edge) Transition time of CLK (Rise and Fall) CAS to CAS Delay time Data output hold time Data output low impedance Row cycle time RAS to CAS delay A.C. Parameter
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
AC Characteristics : (Ta = 0 to 70C V DD = 3.3V 0.3V, VSS = 0V)
-75 Min. 60 20 15 15 37.5 CL2 CL3 7.5 7.5 2.25 2.25 CL2 CL3 1 1 2.5 0 CL2 CL3 1 0.5 1 2 2 2 CL2 CL3 2clk+tRP 2clk+tRP 1 64 4 4 2 1 1 2 2 1 5 5 10 1 1 3 0 100,000 Max. Min. 70 20 20 20 50 10 10 3 3
-8H Max. unit note
Precharge to refresh/row activate command Row activate to row activate delay Row activate to precharge time
ns
100,000
ns 6 6 10 CLK
6 6 ns 9
CLK ns CLK CLK ns CLK 64 ms
1clk+tRP 1clk+tRP 1
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Basic Features and Function Description 1.Simplified State Diagram
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Self
Refresh
try en it ex
LF SE
Mode Register Set
MRS
IDLE
LF SE
REF
AUTO Refresh
CK E
CK E
Power Down
ROW ACTIVE
BS T
ACT
CKE CKE
Active Power Down
T BS
Au Write to p rec with har ge
e rit W
Write (Write recovery)
Re ad
h wit rge ad cha Re Pre to Au
e rit W
ry ve co re
Read
WRITE SUSPEND
CKE CKE
WRITE
Read (write recovery) Write
R Auto ead w Prec ith harg e
Write with Auto Precharge
ith e d w arg Rea Prech to Au (writ
e re cove ry)
PRE
READ
CKE CKE
READ SUSPEND
Read with Auto Precharge
ter min atio n)
Pre E( PR
WRITEA SUSPEND
CKE CKE
WRITEA
CKE READA CKE
READA SUSPEND
POWER ON
Precharge
Precharge
Automatic sequence Manual input Note: After the AUTO refresh operation, precharge operation is performed automatically and enter the IDLE state.
Document : 1G5-0154
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Pre c
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2. Truth Table 2.1 Command Truth Table
FUNCTION Device deselect No operation Mode register set Bank activate Read Read with auto precharge Write Write with auto precharge Precharge select bank Precharge all banks Burst stop CBR (Auto) refresh Self refresh Symbol DESL NOP MRS ACT READ READA WRIT WRITA PRE PALL BST REF SELF H H H H H H H H H H H H H
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
CKE n -1 n X X X X X X X X X X X H L CS H L L L L L L L L L L L L RAS X H L L H H H H L L H L L CAS X H L H L L L L H H H L L WE X H L H H H L L L L L H H BA(1) X X L V V V V V V X X X X A10 X X L V L H L H L H X X X
A11 A9 - A0
X X V V V V V V X X X X X
2.2 DQM Truth Table
CKE FUNCTION Data write/output enable Data mask/output disable Upper byte write enable/output enable Lower byte write enable/output enable Upper byte write inhibit/output disable Lower byte write inhibit/output disable Symbol ENB MASK ENBU ENBL MASKU MASKL n -1 H H H H H H n -1 X X X X X X L X H X U L H X L X H DQM L
2.3 CKE Truth Table
CKE Current State Activating Any Clock suspend Idle Idle Self refresh Idle Power down Function Clock suspend mode entry Clock suspend Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit REF SELF Symbol n-1 H L L H H L L H L n L L H H L H H L H CS X X X L L L H X X RAS X X X L L H X X X CAS X X X L L H X X X WE X X X H H H X X X Add ress X X X X X X X X X
H : High level, L : Low level X : High or Low level (Don' care), V : Valid Data input t
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2.4 Operative Command Table Notes 1
Current state Idle CS RAS CAS WE H L L L L L L L Row active H L L L L L L L Read H L L L L L L L L Write H L L L L L L L L X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L X X Address
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
(1/3)
Command DESL NOP or BST
Action Nop or Power down Nop or Power down
Notes 2 2 3 3
BA, CA, A10 READ/READA ILLEGAL BA, CA, A10 WRIT/WRITA BR, RA BA, A10 X Op - Code X X ACT PRE/PALL REF/SELF MPS DESL NOP or BST ILLEGAL Row active Nop Refresh or Self refresh Mode register access Nop Nop
4
BA, CA, A10 READ/READA Begin read : Determine AP BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code X X X ACT PRE/PALL REF/SELF MRS DESL NOP BST Begin write : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst end
5 5 3 6
Row active Row active
7 7,8 3
Row active
BA, CA, A10 READ/READA Term burst, new read : Determine AP BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code X X X ACT PRE/PALL REF/SELF MRS DESL NOP BST Term burst, start write : Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop
Write recovering Write recovering
7,8 7 3 9
Row active
BA, CA, A10 READ/READA Term burst, start read : determine AP BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code ACT PRE/PALL REF/SELF MRS Term burst, new write : Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL
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Current state Read with auto precharge CS RAS CA H L L L L L L L L Write with auto precharge H L L L L L L L L precharging H L L L L L L L L Row activating H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X X Address
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
(2/3)
Command DESL NOP BST
Action Continue burst to end Continue burst to end
Notes

Prcharging Prcharging
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code X X X ACT PRE/PALL PEF/SELF MRS DESL NOP BST
Illegal for single bank, but legal for multibanks interleave Illegal for single bank, but legal for multibanks interleave ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Write recovering with auto precharge Continue burst to end Write recovering with auto precharge ILLEGAL Illegal for single bank, but legal for multibanks interleave Illegal for single bank, but legal for multibanks interleave ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP 3 3
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code X X X ACT PRE/PALL PEF/SELF MRS DESL NOP BST
3 3
Enter idle after tRP Nop Enter idle after tRP
Nop ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP ILLEGAL ILLEGAL Nop Enter row active idle after tRCD Nop Enter row active idle after tRCD Nop Enter row active idle after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 3 3 3,9 3 3 3 3
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code X X X ACT PRE/PALL PEF/SELF MRS DESL NOP BST
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code ACT PRE/PALL PEF/SELF MRS
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Current state Write recovering CS H L L L L L L L L Write recovering with auto precharge H L L L L L L L L Auto Refreshing H L L L L Mode register setting H L L L L RAS X H H H H L L L L X H H H H L L L L X H H L L X H H H L CA X H H L L H H L L X H H L L H H L L X H L H L X H H L X WE X H L H L H L H L X H L H L H L H L X X X X X X H L X X X X X
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
(3/3)
Address
Command DESL NOP BST Nop Nop Nop
Action
Notes

Enter row active after tDPL Enter row active after tDPL Enter row active after tDPL 8 3 3
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code X X X ACT PRE/PALL PEF/SELF MRS DESL NOP BST
Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Nop Nop

Enter precharge after tDPL Enter precharge after tDPL
Enter precharge after tDPL
3,8 3 3 3
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 X Op - Code X X X X X X X X X X ACT REF/PALL REF/SELF MRS DESL NOP/BST READ/WRIT
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after t RC Nop Enter idle after t RC ILLEGAL
ACT/PRE/PALL ILLEGAL REF/SELF/MRS ILLEGAL DESL NOP BST READ/WRITE ACT/PRE/ PALL/ Nop Nop

Enter idle after 2 Clocks Enter idle after 2 Clocks
ILLEGAL ILLEGAL ILLEGAL
Note 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don' satisfy t DPL. t 10. Illegal if tRRD is not satisfied. 11. Illegal for single bank, but for multibanks interleave
Document : 1G5-0154 Rev.1 Page 12
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n-1 n X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE Note 1 CKE RAS CS RAS CAS Current state
Self refresh (S.R.)
H L L L L L
WE X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X
Address X X X X X X X X X X X X X X X X X X
Action INVALID, CLK (n-1)would exit S.R. S.R. Recovery S.R. Recovery ILLEGAL ILLEGAL Maintain S.R. Idle after tRC Idle after tRC ILLEGAL ILLEGAL Begin clock suspend next cycle Begin clock suspend next cycle ILLEGAL ILLEGAL Exit clock suspend next cycle Maintain clock suspend INVALID, CLK(n-1) would exit P.D. EXIT P.D. Idle Maintain power down mode Refer to operations in Operative Command Table
Notes
X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X
2 2
Self refresh recovery
H H H H H H H H L L
5 5
2
Power down (P.D.) Both banks idle
H L L H H H H H H H H H H L
2
Refer to operations in Operative Command Table Refer to operations in Operative Command Table X Auto Refresh Op-Code Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh
X
3
Op-Code Refer to operations in Operative Command Table X X X Power down Refer to operations in Operative Command Table Begin clock suspend next cycle 3
Any state other than listed above
H H L L
4
X X X Exit clock suspend next cycle X X X Maintain clock suspend Note 1. H : Hight level, L : low level, X : High or low level (Don't care) 2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5. IIIegal if tSREX is not satisfied.
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5.Mode Register (Address Input for Mode Set) 13 12 11 000 13 12 xx 13 12 xx 11 x 11 x 6 6 6 10 0 10 x 10 x 9 0 9 1 9 0 8 0 8 0 8 0 7 1 7 0 7 0 5 54 LTMODE 4 LTMODE 5 3 3
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
43 2 Reserved 2 WT 2 WT
1 1
0
JEDEC Standard Test Set
0 BL
Burst Read and Single Write (for Write Through Cache)
1
0 BL
Burst Read and Burst Write
X = Don' care t
Bits2 - 0 WT = 0 WT = 1 1 1 000 001 010 Burst length 011 100 101 110 111 Wrap type 0 1
2 4 8 R R R
Full page
2 4 8 R R R R
Sequential Interleave
Bits6 - 4 CAS Iatency R 000 001 010 Latency mode 011 100 101 110 111
R 2 3 R R R
R
Remark R : Reserved
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5.1 Burst Length and Sequence
(Burst of Two) Starting Address (column address A0, binary) 0 1 (Burst of Four) Starting Address (column address A1 - A0, binary) 00 01 10 11 (Burst of Eight) Starting Address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Sequential Addressing Sequence (decimal) 0, 1 1, 0
Interleave Addressing Sequence (decimal) 0, 1 1, 0
Sequential Addressing Sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2
Interleave Addressing Sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
Sequential Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1 ,2 4, 5, 6, 7, 0, 1, 2, 3 5, 6 ,7, 0, 1, 2, 3, 4 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 7, 0, 1, 2, 3, 4, 5, 6
Interleave Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 2048 / 1024 / 512 for 32M x 4 / 16M x 8 / 8M X16 devices, respectively.
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6 Address Bits of Bank-Select and precharge 6.1 Quad banks controlled by A12 & A13
(Activate command)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
A12 0 0 1 1
A13 0 1 0 1
Result Select Bank A "Activate " command Select Bank B "Activate" command Select Bank C "Activate" command Select Bank D "Activate" command
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Row (Precharge command)
A10 0 0 0 0 1
A12 A13 Result 0 0 1 1 X 0 1 0 1 X Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks
0 1 Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (CAS strobes)
Disables Auto - Precharge (End of Burst) Enables Auto - Precharge (End of Burst) A12 0 0 1 1 A13 0 1 0 1 Result Enables Read/Write commands for Bank A Enables Read/Write commands for Bank B Enables Read/Write commands for Bank C Enables Read/Write commands for Bank D
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7.Precharge
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
The precharge command can be asserted anytime after tRAS(min) is satisfied. Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
PrechargeE
T0
T1
T2
T3
T4
T5
T6
Burst lengh=4 T7
CLK Command Read PRE CAS latency = 2 DQ Q0 Q1 Q2 Q3 Hi - Z
Command CAS latency = 3 DQ
Read
PRE
Q0
Q1
Q2
Q3
Hi - Z
CAS latency = 2 : One clock earlier than the last output data. 3 : Two clocks earlier than the last output data. (tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter "t DPL" must be satisfied. The tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be calculated by dividing tDPL(min.) by the clock cycle time. In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. CAS latency 2 3 Read -1 -2 Write + tDPL(min.) + tDPL(min.)
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8.Auto Precharge
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically after the burst access. In the write cycle, t DAL(min.) must be satisfied before asserting the next activate command to the bank being precharged. When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has been satisfied. A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge command if the device is programmed for full page burst read or write cycles. The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode register and whether the cycle is read or write. 8.1 Read with Auto Precharge During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last word output.
READ with AUTO PRECHARGE
Burst lengh = 4 T0 T1 T2 T3
T4
T5
T6
T7
T8
CLK
No New Command to Bank B
Command
READA B
Auto precharge starts
CAS latency = 2 DQ QB0 QB1 QB2 QB3 Hi - Z
No New Command to Bank B
Auto precharge starts Command CAS latency = 3 DQ Remark READA means READ with AUTO PRECHARGE QB0 QB1 QB2 QB3 Hi - Z
READA B
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8.2 Write with Auto Precharge
after the last data word input to the device.
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.)
WRITE with AUTO PRECHRGE
Burst lengh = 4 T0 CLK
No New Command to Bank B
T1
T2
T3
T4
T5
T6
T7
T8
Command
WRITA B
AUTO PRECHARGE starts
CAS latency = 2 DQ
DB0 DB1 DB2
tDPL
Hi - Z_
DB3
No New Command to Bank B
Command CAS latency = 3 DQ
AUTO PRECHARGE starts
WRITA B
tDPL
Hi - Z
DB0
DB1
DB2
DB3
Remark WRITA means WRITE with AUTO Precharge
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference. CAS latency 2 3 Read -1 -2 Write + tDPL(min.) + tDPL(min.)
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charge scheduled time would not be changed.
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
8.3 Multibank Operation- Read with Auto Precharge During a READA cycle interrupted by a Read, Write command of another banks, the auto-pre-
Multibank Operation
Burst lengh=8
T0
CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12 T13 T14
Auto precharge bank A starts
Command CAS latency=2 Hi-Z DQ
QA0 QA1 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7
READA A
Read B
Auto precharge bank A starts
Command CAS latency=3 Hi-Z
QA0 QA1 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7
READA A
Read B
DQ
Similiar top.21
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Multibank Operation
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
8.4 Multibank Operation- Write with Auto Precharge During a WRITEA cycle interrupted by a Read, Write command of another banks, the auto-precharge scheduled time would not be changed.
Burst lengh=8
T0
CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Auto precharge bank A starts
Command CAS latency=2 Hi-Z WRITA A Read B
DQ
DA0
DA1
DB0
DB1
DB2
DB3
DB4
DB5
Auto precharge bank A starts
Command CAS latency=3 Hi-Z WRITA A Read B
DQ
DA0
DA1
DB0
DB1
DB2
DB3
DB4
Multibank Operation
Burst lengh=8
T0
CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Auto precharge bank A starts
Command CAS latency=2 DQ DA0 DA1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Hi-Z WRITA A Write B
Auto precharge bank A starts
Command CAS latency=3 DQ DA1 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Hi-Z WRITA A Write B
DA0
DB0
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9.Read/Write Command Interval 9.1 Read to Read command interval
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ. Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK Read A Read B
Command
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
9.2 Write to Write Command Interval During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will begin with a new write command. WRITE will be interrupted by another WRITE. Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK Write A Write B
Command
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
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WRITE to READ Command Interval
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
9.3 Write to Read Command Interval The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK 1 cycle Command CAS latency=2 Hi-Z WRITE A Read B
DQ
DA0
QB0
QB1
QB2
QB3
Command
Write A
Read B
CAS latency=3 DQ DA0 Hi-Z QB0 QB1 QB2 QB3
9.4 Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data bus must be Hi-Z using DQM before Write.
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READ to WRITE Command Interval
T0 T1 T2
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
T3
T4
T5
T6
T7
CAS latency=2 T8
CLK
Command
Read
Write
DQM
DQ
Hi-Z
D0
D1
D2
D3
1 cycle
T0
T1
T2
T3
T4
T5
T6
T7
Burst length=8, CAS latency=2 T8 T9
CLK
Command
Read
Write
DQM
DQ
Q0
Q1
Q2 Hi-Z is necessary
D0
D1
D2
example: Burst length=4, CAS latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
Command
Read
Write
DQM
DQ Q2 Hi-Z is necessary The minimum command interval = (4+1) cycles D0 D1 D2
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10.BURST Termination 10.1 BURST Stop Command
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop command and the other is the precharge command.
During a read burst. when the burst stop command is asserted, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command. During a write burst, when the burst stop command is asserted, any data provided at that cycle will not be written. The burst write is effectively terminated and no further data can be written until a new write command is asserted.
Burst Termination
Burst lengh=X, CAS Intency=2,3 T7 T6
T0
T1
T2
T3
T4
T5
CLK BST
Command
Read
CAS latency=2 DQ
Q0
Q1
Q2
Hi-Z
CAS latency=3 DQ
Q0
Q1
Q2
Hi-Z
Remark BST: Burst stop command
Burst lengh=X, CAS latency=2,3 T7 T6
T0
T1
T2
T3
T4
T5
CLK BST
Command
Write
CAS latency=2,3 Q0 DQ Q0 Q1 Q2 Hi-Z_
Remark BST: Burst command
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10.2 PRECHARGE TERMINATION
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
10.2.1 PRECHARGE TERMINATION in READ Cycle During READ cycle, the burst read operation is terminated by a precharge command. When the precharge command is asserted, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. When CAS latency is 2,the read data will remain valid until one clock after the precharge command. When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
T0
T1
T2
T3
T4
T5
T6
T7
Burst lengh= X T8
CLK
Command
Read
PRE
ACT
CAS latency=2 DQ Q0 Q1 Q2 Q3 tRP command Read PRE tRP Hi-Z ACT Hi-Z
CAS latency=3 DQ
Q0
Q1
Q2
Q3
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nated and precharge starts.
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is asserted, the burst write operation is termi-
The same bank can be activated again after t RP from the precharge command. The DQM must be high to mask invalid data in. During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X T8
T0 CLK Command CAS latency = 2 DQM DQ D0 Write
T1
T2
T3
T4
T5
T6
T7
PRE
ACT
D1
D2
D3
D4 tRP
Hi - Z
command CAS latency = 3
DQM
Write
PRE
ACT
DQ
D0
D1
D2
D3
D4
Hi - Z tRP
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Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
,
Timing Diagram
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Mode Register Set
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
t RSC
CS
RAS
CAS
WE
BS
A10
Address Key
ADD
DQM
t RP
DQ
Hi-Z
Precharge Command All Banks
Mode Register Set Command
Command
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AC Parameters for Write Timing (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5
T6 T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CH t CL t CMS t CMH t CK2 Begin Auto Precharge Begin Auto Precharge Bank A Bank B (Bank D)
CKE
t CKS
t CKH
CS
RAS
CAS
WE
BS
A10
t AS tAH
ADD
DQM
tRCD
DQ
t RRD tRC
tDAL
tDS t DH t DPL t RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank A Command Bank B (Bank D) Bank B Bank A (Bank D)
Write without Auto Precharge Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B (Bank D)
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AC Parameters for Write Timing (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3,4 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CLK
t CL t CH t CK3 t CMS t CMH Begin Auto Precharge Begin Auto Precharge Bank A Bank B (Bank D) t CKH
CKE
t CKS
CS
RAS
CAS
WE
BS
A10
t AS t AH
ADD
DQM
tRCD
DQ
t RRD
t
t DAL RC
tDS t DH t DPL t RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3
QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write with Activate Write with Auto Precharge Command Auto Precharge Command Bank B Command Bank A Bank B (Bank D) (Bank D)
Activate Command Bank A
Write without Auto Precharge Command Bank A
Precharge Command Bank A
Activate Command Bank A
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AC Parameters for Read Timing (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=2, CAS Latency=2
T0 CLK
tCH tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCK2 tCMS t CMH Begin Auto Precharge Bank B (Bank D) t CKH
CKE
tCKS
CS
RAS
CAS
WE
BS
A10
tAS tAH
ADD
tRRD tRAS tRC
DQM
t AC2 tLZ tAC2 tOH QAa0
t RCD
tHZ tOH QAa1 QBa0
tRP tHZ QBa1
DQ
Hi-Z
Activate Command Bank A
Read Command Bank A
Activate Command Bank B (Bank D)
Read with Auto Precharge Command Bank B (Bank D)
Precharge Command Bank A
Activate Command Bank A
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AC Parameters for Read Timing (2 of 2)
T0 CLK
t CH tCL t CK3 t CMS t CMH
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=2, CAS Latency=3 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
CKE
tCKS
Begin Auto Precharge Bank B (Bank D)
t CKH
CS
RAS
CAS
WE
BS
A10
t AH t AS
ADD
t RRD t RAS t RC t RP
DQM
t RCD
tAC3 tLZ
tAC3 tOH
tHZ tOH
QAa1 QBa0
t
HZ
DQ
Hi-Z
QAa0
QBa1
Activate Command Bank A
Read Command Bank A
Activate Command Bank B (Bank D)
Read with Precharge Auto Precharge Command Command Bank A Bank B (Bank D)
Activate Command Bank A
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Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK CKE
High level is required t RSC Minimum of 2 Refresh Cycles are required
CS
RAS
CAS
WE
BS
A10
Address Key
ADD
DQM
High Level is Necessary t RP t RC
DQ
Hi-Z
Precharge Inputs Command All Banks must be stable for 100us
1st Auto Refresh Command
2nd Auto Refresh Command
Mode Register Set Command
Command
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Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
t HZ
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Read Command Bank A
Clock Suspended 1 Cycle
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
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Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK3
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
t HZ
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Read Command Bank A
Clock Suspended 1 Cycles
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
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Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Write (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3
Activate Command Bank A
Clock Suspended 1 Cycle Write Command Bank A
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
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Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Write (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 CLK
t CK
T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3
Activate Command Bank A
Clock Suspended 1 Cycle Write Command Bank A
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
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Power Down Mode and Clock Mask
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
CLK can be Stopped*
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t t CKS
CKH
t CKS
CKE
VALID
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
t Hi-Z
QAa0 QAa1 QAa2 QAa3
HZ
DQ
Activate Command Bank A
ACTIVE STANDBY
Read Command Bank A Clock Mask Start Clock Mask End
Precharge Command Power Down Mode Entry
Precharge Standby
Power Down Mode Entry
Power Down Mode Exit
Power Down Mode Exit Command
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Auto Refresh (CBR)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
DQM
t RP t RC t RC
Q0 Q1 Q2 Q3
DQ
Hi-Z
Precharge CBR Refresh Command Command All Banks
CBR Refresh Command
Activate Read Command Command
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Self Refresh (Entry and Exit)
CLK can be Stopped*
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t SRX
t SRX
t CKS
CKE
t CKS
CS
RAS
CAS
WE
BS
A10
ADD
t RC t RC
DQM
DQ
Hi-Z
All Banks must be idle
Self refresh Entry
Self Refresh Exit
Self Refresh Entry Self Refresh Exit
Activate Command
* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
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Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Random Column Read (Page Within same Bank)(1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
RAd RAa
ADD
RAa
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
QAd0 QAd1 QAd2 QAd3
Precharge Command Bank A
Read Command Bank A
Read Read Command Command Bank A Bank A
Precharge Activate Read Command Command Command Bank A Bank A Bank A
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Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Random Column Read (Page Within same Bank)(2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK3
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
RAd
ADD
RAa
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Activate Command Bank A
Read Command Bank A
Read Read Command Command Bank A Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Document : 1G5-0154
Rev.1
Page 43
VIS
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Random Column Write (Page Within same Bank) (1 of 2)
Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Rd
ADD
Ra
Ca
Cb
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Da1
Da2
Da3
Db0
Db1
Dc0
Dc1
Dc2
Dc3
Dd0
Dd1
Dd2
Dd3
Activate Command Bank B (Bank D)
Write Command Bank B (Bank D)
Write Write Command Command Bank B Bank B (Bank D) (Bank D)
Precharge Activate Write Command Command Command Bank B Bank B Bank B (Bank D) (Bank D) (Bank D)
Document : 1G5-0154
Rev.1
Page 44
VIS
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Random Column Write (Page Within same Bank) (1 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Rd
ADD
Ra
Ca
Cb
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Da1
Da2
Da3
Db0
Db1
Dc0
Dc1
Dc2
Dc3
Dd0
Dd1
Activate Command Bank B (Bank D)
Write Command Bank B (Bank D)
Write Command Bank B (Bank D)
Write Command Bank B (Bank D)
Precharge Command Bank B (Bank D)
Activate Command Bank B (Bank D)
Write Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 45
VIS
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks)(1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
BS
A10
ADD
t t AC2 t RP
DQM
RCD
DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
QBb0 QBb1
Activate Command Bank B (Bank D)
Read Command Bank B (Bank D)
Activate Command Bank A
Precharge Active Command Command Bank B Bank B (Bank D) (Bank D) Read Command Bank A
Read Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 46
VIS
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Random Row Read (Interleaving Banks) (2 of 3)
Burs tLength=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
BS
A10
ADD
t t RCD AC3 t RP
DQM
DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0
Activate Command Bank B (Bank D)
Read Command Bank B (Bank D)
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B (Bank D)
Activate Command Bank B (Bank D)
Read Precharge Command Command Bank B Bank A (Bank D)
Document : 1G5-0154
Rev.1
Page 47
VIS
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
BS
A10
ADD
DQM
t RCD
t DPL
t
RP
t DPL
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAb0 QAb1 QAb2 QAb3 QAb4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B (Bank D)
Precharge Active Command Command Bank A Bank A Write Command Bank B (Bank D)
Write Command Bank A Precharge Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 48
VIS
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Random Row Write (Interleaving Banks) (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
BS
A10
ADD
RBa
DQM
t RCD
t DPL
t RP
t DPL
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBb7 QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B (Bank D)
Write Command Bank B (Bank D)
Precharge Command Bank A
Activate Command Bank A
Precharge Write Command Command Bank B Bank A (Bank D)
Document : 1G5-0154
Rev.1
Page 49
VIS
Read and Write Cycle (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
CAb
CAc
DQM
Hi-Z
DQ
QAa0 QAa1 QAa2 QAa3
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Command Bank A
Write Command Bank A
The Write Data Write Command is Masked with a Bank A Zero Clock latency
Read Command Bank A
The Read Data is Masked with Two Clocks Latency
Document : 1G5-0154
Rev.1
Page 50
VIS
Read and Write Cycle (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
CAb
CAc
DQM
Hi-Z
QAa0 QAa1 QAa2 QAa3
DQ
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Command Bank A
Read Command Bank A
Write The Write Data Read Command is Masked with a Command Bank A Bank A Zero Clock
Latency
The Read Data is Masked with a Two Clock Latency
Document : 1G5-0154
Rev.1
Page 51
VIS
Interleaved Column Read Cycle (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
ADD
Ra
Cb
Ra
Ca
Cb
Cc
Cb
Cd
DQM
t
RCD
t AC2
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate Command Bank A
Read Read Read Activate Read Read Read Command Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank B Bank B Bank B (Bank D) (Bank D) (Bank D) (Bank D) (Bank D) Precharge Command Bank A
Precharge Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 52
VIS
Interleaved Column Read Cycle (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
DQM
t RCD t RRD t AC3
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Read Command Bank A Activate Command Bank B (Bank D)
Read Read Read Read Precharge Precharge Command Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Bank A (Bank D) (Bank D) (Bank D) (Bank D)
Document : 1G5-0154
Rev.1
Page 53
VIS
Interleaved Column Write Cycle (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
Cb
DQM
t RCD
t RP
t DPL
t Hi-Z
RRD
DQ
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2 DBd3
Activate Write Write Write Write Write Activate Command Command Command Command Command Command Command Bank B Bank B Bank A Bank A Bank B Bank B Bank A (Bank D) (Bank D) (Bank D) (Bank D)
Precharge Command Bank A Write Command Bank B (Bank D)
Precharge Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 54
VIS
Interleaved Column Write Cycle (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK
CKE CS
RAS
CAS
WE
BS
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
Cd
DQM
t RCD
t DPL
t DPL
t Hi-Z
RRD
t RP
DQ
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate Command Bank A
Write Command Bank A Activate Command Bank B (Bank D)
Write Write Write Write Write Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B (Bank D) (Bank D) (Bank D) (Bank D) Precharge Command Bank A
Precharge Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 55
VIS
Auto Precharge after Read Burst (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK2
Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank A Start Auto Precharge Bank B (Bank D)
CKE
High
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
Rc
ADD
Ra
Ca
Ra
Ca
Cb
Rb
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2
Activate Read Activate Read with Command Command Command Auto Precharge Bank A Bank A Bank B Command (Bank D) Bank B (Bank D)
Read with Auto Precharge Command Bank A
Activate Command Read with Bank A Auto Precharge Command Read with Activate Bank B Auto Precharge Command (Bank D) Command Bank B Bank A (Bank D)
Document : 1G5-0154
Rev.1
Page 56
VIS
Auto Precharge after Write Burst (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK3
Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank A Start Auto Precharge Bank B (Bank D)
CKE
High
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2
Activate Command Bank A
Activate Command Bank B (Bank D) Read Command Bank A
Read with Auto Precharge Command Bank B (Bank D)
Read with Auto Precharge Command Bank A
Activate Command Bank B (Bank D)
Write with Auto precharge Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 57
VIS
Auto Precharge after Write Burst (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank A Start Auto Precharge Bank B (Bank D)
CKE
High
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
Rc
ADD
Ra
Ca
Ra
Ca
Cb
Rb
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3
Activate Write Write with Activate Command Command Command Auto Precharge Command Bank A Bank B Bank A Bank B (Bank D) (Bank D)
Activate Write with Activate Command Auto Precharge Command Bank A Command Bank B Write with Bank A (Bank D) Auto Precharge Write with Bank A Auto Precharge Command Bank B (Bank D)
Start Auto Precharge Bank A
Document : 1G5-0154
Rev.1
Page 58
VIS
Auto Precharge after Write Burst (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t
CK
Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank A Start Auto Precharge Bank B (Bank D)
CKE
High
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3
Activate Command Bank A
Activate Command Bank B (Bank D) Read Command Bank A
Read with Auto Precharge Command Bank B (Bank D)
Read with Auto Precharge Command Bank A
Activate Command Bank B (Bank D)
Write with Auto precharge Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 59
VIS
Full Page Read Cycle (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
t RP
DQ
Hi-Z
QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6
Activate Command Bank A
Read Command Bank A
Activate Command Bank B (Bank D)
Read Command Bank B (Bank D) The burst counter wraps from the highest order page address back to zero during this time interval
Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address
Precharge Command Bank B (Bank D) Burst Stop Command
Activate Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 60
VIS
Full Page Read Cycle (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
DQ
Hi-Z
QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Activate Command Bank A
Read Command Bank A
Activate Command Bank B (Bank D)
Full page burst operation Read does not teminate when Command the burst length is satisfied; Bank B the burst counter increments (Bank D) and continues bursting The burst counter wraps beginning with the starting from the highest order address page address back to zero during this time interval
Precharge Command Bank B (Bank D) Burst Stop Command
Activate Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 61
VIS
Full Page Write Cycle (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
t BDL
DQ
Hi-Z
QAa QAa+1 QAa+2 QAa+3 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 QBa+6
Activate Command Bank A
Write Command Bank A
Activate Command Bank B (Bank D) The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B (Bank D)
Data is ignored Precharge Command Bank B (Bank D) Burst Stop Command
Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address
Activate Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 62
VIS
Full Page Write Cycle (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
tBDL Data is ignored.
DQ
Hi-Z
DAa DAa+1 DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4 DBa+5
Activate Command Bank A
Write Command Bank A
Activate Command Bank B (Bank D) The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B (Bank D) Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address
Precharge Command Bank B (Bank D) Burst Stop Command
Activate Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 63
VIS
Byte Write Operation
T0 T1 T2 T3 T4 T5 T6 T7
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length = 4, CAS Latency = 2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE CS
High
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
CAb
CAz
LDQM
UDQM
DQ0~DQ7
Hi-Z
DQ8~DQ15 Hi-Z
Activate Command Bank A Read Command Bank A Upper Byte is masked Lower Byte is masked Write Command Bank A Read Write Upper Command is masked Bank A Lower Byte is masked
Lower Byte is masked
Document : 1G5-0154
Rev.1
Page 64
VIS
Burst Read and Single Write Operation
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2 High
CKE CS
RAS
CAS
WE
BS
A10
RAa
ADD
RAa
CAa
CAb
CAc
CAd
CAe
LDQM
UDQM
DQ0~DQ7
Hi-Z
DQ8~DQ15 Hi-Z
Activate Command Bank A Read Command Bank A Read Single Write Single Write Command Command Command Bank A Bank A Bank A Lower Byte is masked Upper Byte is masked
Single Write Command Bank A
Lower Byte is masked
Document : 1G5-0154
Rev.1
Page 65
VIS
Full Page Random Column Read
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ra
Ca
Ca
Cb
Cb
Cc
Cc
Rb
t RP
DQM DQ
Hi-Z
QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Activate Command Bank A
Activate Command Bank B (Bank D)
Read Read Command Command Bank B Bank B (Bank D) (Bank D) Read Read Command Command Bank A Bank A
Read Command Bank A
Read Command Bank B (Bank D)
Precharge Command Bank B (Bank D) (Precharge Termination) Activate Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 66
VIS
Full Page Random Column Write
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ra
Ca
Ca
Cb
Cb
Cc
Cc
Rb
t RP
DQM
DQ
Hi-Z
QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Activate Command Bank A
Activate Command Bank B (Bank D)
Write Write Command Command Bank B Bank B (Bank D) (Bank D) Write Write Command Command Bank A Bank A
Write Command Bank A
Write Command Bank B (Bank D)
Precharge Command Bank B (Bank D) (Precharge Termination) Write Data is masked Activate Command Bank B (Bank D)
Document : 1G5-0154
Rev.1
Page 67
VIS
Precharge Termination of a Burst (1 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4,8 or Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
BS
A10
RAa
RAb
RAc
ADD
RAa
CAa
RAb
CAb
RAc
CAc
t
DPL
t
RP
t
RP
t
RP
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 Da3 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Write Burst. Write data is masked.
Precharge Termination of a Read Burst.
Document : 1G5-0154
Rev.1
Page 68
VIS
Precharge Termination of a Burst (2 of 2)
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4,8 or Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK3
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
BS
A10
RAa
RAb
RAc
ADD
RAa
CAa
RAb
CAb
RAc
t DPL
t
RP
t
RAS
t
RP
DQM
t
RCD
DQ
Hi-Z
DAa0 DAa1 QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Activate Command Bank A
Activate Command Bank A
Write Data is masked
Precharge Termination of a Write Burst.
Precharge Termination of a Read Burst.
Document : 1G5-0154
Rev.1
Page 69

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